# SPHBM4: The HBM Packaging Playbook Is Changing

### How a Standard That Bypasses the Silicon Interposer Reshapes the Memory and Foundry Order

In June 2026, JEDEC published a new HBM standard.

JESD330-4, formally the _**S** tandard **P** ackage **H** igh **B** andwidth **M** emory_, or SPHBM4 for short.

The name carries “HBM,” so the instinct is to picture faster or larger next-generation memory. But this standard does not touch DRAM performance at all. What it changes is not the memory itself but the way memory attaches to the GPU, namely the packaging.

Why does that matter.

Ask which resource in an AI accelerator is the most expensive and the most scarce, and most people think of HBM. But even with HBM in hand, if the packaging that attaches it to the GPU is blocked, the accelerator does not ship.

Packaging draws less attention than HBM, yet it is just as much a bottleneck that decides what ships. Packaging accounts for a single-digit to low-teens share of an accelerator’s total cost, but its capacity governs shipment volume. That is why a standard that changes the attach method goes beyond a simple component spec.

If SPHBM4 takes hold, the fallout will not stop at the memory companies. As value concentrated in packaging shifts to other layers, the positions of Samsung Electronics and SK hynix, and of TSMC and NVIDIA too, all get shaken.

This piece follows what SPHBM4 changes technically, why it arrived now, which layer of the packaging supply chain its value migrates to as a result, and within that migration, where the market has already priced things in versus where the gaps remain.

It should serve as a guide both for engineers who want to understand semiconductor packaging and HBM structure precisely, and for investors trying to map the reshaping of the AI infrastructure supply chain.

**Contents**

1. The DRAM stays, only the bottom chip changes
2. What SPHBM4 targets is the packaging bottleneck
3. The center of gravity moves from interposer to base die
4. How to read this standard
5. The standard is out, adoption comes next

* * *

# The DRAM stays, only the bottom chip changes

It is an HBM that reuses HBM4 DRAM as is, swapping only the single bottommost chip, so that the HBM can attach directly to the package substrate instead of sitting on a large silicon interposer next to the GPU. Let me take this one sentence apart word by word.

HBM is memory built by stacking several DRAM dies vertically. Stack them plainly and the top and bottom chips are not connected, so holes are drilled through the chips to run vertical wiring. That wiring is the TSV (Through-Silicon Via). At the very bottom of the stack sits one more chip, which plays the interface role of passing signals between the DRAM stacked above and the GPU outside. The controller that issues reads and writes sits on the GPU side, and this chip is closer to a middle bridge that receives those commands and relays them to the DRAM. JEDEC calls it the buffer die, the industry calls it the base die, and they are the same chip. This piece uses base die.

What sets SPHBM4 apart from HBM4 is exactly one thing. The DRAM stacked above is reused straight from HBM4, and only the base die is newly designed. For a memory company, that means reusing DRAM it already makes and just swapping the bottom chip, so as new standards go, the barrier to entry is low.

### Cut I/O to a quarter, raise speed fourfold

The heart of SPHBM4’s redesigned base die is a sharp cut in pins. Let me start with how it cuts pins yet holds performance. Bandwidth, the amount of data exchanged per second, is set by two things: the number of paths the data travels through (I/O pins), and the speed each pin carries. The product of the two is the total bandwidth.

```plaintext
bandwidth = pin count × per-pin speed
```

HBM4 went the way of adding paths, with 2,048 data signal pins.

Lay down a great many paths and push a lot through at once. SPHBM4 cuts paths and makes up for it with speed, reducing pins from 2,048 to 512, a quarter.[1]

With paths cut to a quarter, leaving it there would drop bandwidth to a quarter too, so it offsets this by raising each pin’s speed fourfold. Paths at a quarter, per-path speed four times. Multiply and it lands back in place, so even with a quarter of the pins the total bandwidth reaches the same level as HBM4.

The way to push each pin’s speed up fourfold is serialization. Where before four pins each sent one slice of data simultaneously, serialization packs those four slices into one pin and sends them out in sequence at four times the speed. One pin does the work of four, so it is called 4:1 serialization, and the circuit that bundles and unbundles the data this way is the SerDes. When the JEDEC document writes of reducing 64 bits per channel to 16 bits and running them four times faster, it is describing the same thing.

One question remains.

_If the bandwidth ends up the same anyway, why bother cutting pins?_

### The pins were cut because of the substrate

Cutting pins leaves bandwidth unchanged, because speed makes up for it. What cutting pins buys is not bandwidth but the ability to attach memory at a cheaper spot.

To understand this, the two layers inside the package have to be told apart first. One is the interposer, a thin board in the middle that links HBM and GPU, made of silicon until now and therefore expensive. The other is the package substrate beneath it, the bottom outer board that carries the whole assembly, made of cheap organic material from the start. HBM4 placed memory on the upper silicon interposer. SPHBM4 skips that interposer and seats memory directly on the lower organic substrate.

Why did HBM4 have to go through the expensive interposer while SPHBM4 can skip it?

Pin count drew the line.

Chip and substrate connect through small bumps planted under the chip. One bump per pin, so more pins means cramming more bumps into a fixed chip area, and the spacing between bumps narrows. This spacing is the bump pitch. The bump pitch a substrate can take is set by how finely signal wiring can be drawn on it. Silicon uses the same lithography process as semiconductors to draw wiring down to around one micron, handling tight spacing in the single-micron range, while organic substrate plates and etches copper, leaving wiring widths in the tens of microns that can only take coarse spacing.

HBM4 has 2,048 pins, so its bump pitch is very tight, and only silicon takes that spacing. That is why it had to go through the expensive silicon interposer. SPHBM4 cut pins to 512 and widened the spacing. The wider spacing organic substrate can take too, so memory attaches directly to the lower organic substrate without going through a silicon interposer. This is the real reason for cutting pins.

### The burden moves to the base die

The price falls on the base die. The region of the base die that handles signaling is called the PHY, and the HBM’s per-pin speed and total bandwidth ride on this PHY’s performance. SPHBM4 cut paths to a quarter and raised per-pin speed fourfold, so the SerDes inside the PHY has to make and receive signals four times faster.

Raise speed fourfold and problems that were minor in HBM4 grow all at once. The faster the signal, the worse the interference where one bit bleeds into the next (ISI), the jitter where timing wobbles slightly, and the crosstalk that leaks into neighboring paths. To rein this in, more circuitry has to go into the PHY: equalization to correct signals, clock and data recovery (CDR) to restore scrambled timing, and correction circuits to fix errors. As the circuitry grows heavier, power and heat climb along with it.

On top of this there is one more problem specific to SPHBM4. The DRAM signals coming down from above are relatively slow, and the signals the base die sends outward are four times faster. This speed gap has to be bundled, unbundled, and matched inside the base die, which makes the circuit design that handles the conversion and synchronization tricky.

In the end the burden has shifted from substrate to base die. The substrate got cheaper, but the base die has to hold faster and more refined high-speed logic. It moves closer to high-speed communication chip design than to simple memory component design.

Put the other way, SPHBM4’s success or failure rides on who designs this base die well. Beyond the memory manufacturing capability to stack higher and hold yield, the logic design capability to handle high-speed PHY and SerDes is added as a new battleground.

**How this change shakes the order between memory companies and foundries is taken up again later.**