If CoPoS Arrives, Who Makes Money First
If CoPoS Arrives, Who Makes Money First
Reading TSMC's shift to panel packaging through two axes: purity and path survival
In AI chips, packaging has become the process that decides performance. As chip miniaturization hits its limits, the method of binding several chips into one has grown more important, and the standard for that is TSMC's CoWoS. TSMC is now preparing CoPoS as the next step beyond CoWoS. Instead of a round wafer, it places chips on a square panel.
Once CoPoS became a talking point, the market went straight to hunting for glass substrate beneficiaries. The reason was the talk that panels use glass. An earlier piece walked through the technology and supply chain of the glass substrate itself, and this time that same glass steps onto the packaging stage, widening the board by one level.
But two things that actually matter are still undecided. First, where exactly glass fits inside the CoPoS structure has not been fixed. TSMC recently showed the possibility by disclosing glass substrate validation results with Ibiden and Innolux, but in the same announcement it drew a line, saying mass production is still far off. Second, this is not a game TSMC decides alone. Intel and Samsung are each pushing panel packaging and glass in their own way, so even which camp and which method wins is still open.
To put it together, the direction of CoPoS is clear but the path and the timeline are both uncertain. In a situation like this, picking stocks off the single word “glass” leaves you most exposed when glass lands in a different spot than expected, or when mass production slips.
Contents
- The terrain: what CoPoS changes and what it does not
- The map’s two axes: purity and path survival
- The stock map by coordinate
- How to read and track the map
- The risks that shake the map
1. The terrain: what CoPoS changes and what it does not
Before drawing the map, look at the terrain. CoWoS stands for Chip on Wafer on Substrate. The chip sits on an interposer made from a round silicon wafer and that is attached to a substrate. CoPoS is Chip on Panel on Substrate. The middle word changed from Wafer to Panel. Instead of a round wafer, it uses a square panel.
Why square? Area. The chips in AI accelerators keep getting bigger. They are expressed as multiples of the reticle, the unit a single exposure shot covers. Place a package this large on a round 12-inch wafer and the edges go to waste, yielding only four to seven per sheet. A square panel loses less at the edges and pulls far more from the same area. TSMC’s first panel format is 310mm by 310mm, and a roadmap is cited that grows it through 515mm by 510mm up to 750mm by 620mm.
The pilot line gets laid down at the subsidiary VisEra in 2026. By press accounts, small trial production is cited for 2027 and mass production for 2028 to 2029.
That said, reading TSMC’s own comments alongside supply-chain commentary, the weight falls on the view that meaningful mass production needs another two to three years of validation.
First, glass’s position is not yet fixed.
Many explanations say CoPoS uses glass as the interposer, but the wording splits by source. Some see CoPoS as a transition that mixes panelization, redistribution layer (RDL), carrier, and glass or organic material, while others flatly call glass a permanent interposer.
The recent validation mentioned above only deepens this uncertainty. What TSMC validated with Ibiden and Innolux was not an interposer but a 0.8-millimeter glass core substrate, and the program was even named “glass substrate for CoWoS.”
This means it has not yet set in one direction whether glass comes in as an interposer or as a core substrate, and which path reaches mass production first.
Second, the weight is on the timeline slipping.
TSMC Chairman C.C. Wei nailed it down: mass production takes another two to three years and there are no shortcuts.
When glass is used as a thin interposer, its thickness drops to about 400 micrometers, half that of a substrate, making CTE (coefficient of thermal expansion) management tricky, and whatever form it takes, warpage worsens as the panel grows. This physical constraint is repeatedly cited as the biggest barrier to mass production.
So when choosing CoPoS stocks, the question to throw out gets simple. With both glass’s position and the mass-production timeline uncertain, which stock gets hit hard when this transition succeeds, and which one holds even when the transition slips or goes sideways? Split this question into two axes and it becomes a map that lines the stocks up.
2. The map’s two axes: purity and path survival
The horizontal axis is CoPoS purity. It divides whether the company’s demand comes directly from the CoPoS transition, or whether it rides along because AI overall is growing.
The vertical axis is path survival. CoPoS is not the only future of AI packaging. The NVIDIA Rubin Ultra generation goes with a mix of CoWoS and CoPoS, and beyond that even CoWoP (Chip on Wafer on PCB), which drops the substrate and attaches the chip directly to the PCB, gets cited.
Overlay the two axes and the uncertainty from the previous chapter unfolds right onto the coordinates.
This is the answer to the first question of how much does it get hit if it succeeds.
And this is the answer to the second question of whether it holds if things go sideways.
That covers the two axes that frame the map. With the axes drawn, the real question remains: where do the names currently lumped together and traded as "glass plays" actually land on this map? The moment you place each stock at its own coordinate, what to buy and what to avoid comes into focus.