Glass Substrate: The Order the Money Flows In

What CoPoS Has Confirmed, and What It Hasn’t Yet

The verbs in glass substrate news changed this year.

Sentences that read “developing” and “evaluating” through last year have become “entered qualification,” “shipped samples,” “completing the pilot line.”

Absolics is running AMD qualification at its Georgia fab. Samsung Electro-Mechanics reportedly shipped glass substrate samples read as part of Apple’s supply chain. TSMC is moving on a schedule to finish the pilot line for its next-generation panel packaging within the year. Related stocks have already run hard once on this news flow.

But “glass substrate” has become a single basket holding four different things.

Glass core substrate, glass interposer, temporary carrier, and glass fiber cloth.

The four do different jobs inside the package, benefit different companies, and turn into money at different times. The confusion runs deep enough that for the same technology at the same company, different research notes describe the role of glass differently.

The most important thing in glass substrate investing is not which company is good, but which spot you catch and when.

Pick the right company but step in long before the money reaches it, and you have to endure the share price bleeding first through the long gap until results show up. Even within the same glass substrate cycle, the timing when money circulates to raw glass and equipment differs by a year or two from the timing it circulates to the substrate makers.

This piece analyzes, in order, what glass actually does as a component inside the package, how far commercialization has come and who stands where, in what order money flows to each spot in the value chain, and what signal to watch before stepping into each spot.

If you are interested in glass substrate investing, this will surely help.

Table of Contents

1. Why the substrate became the problem
2. The four kinds of glass mixed inside the phrase “glass substrate”
3. How far has commercialization come? 2026 is the year of qual
4. The order the money flows in, and the position map
5. Layer-by-layer checklist: what to watch before stepping in
6. The leading indicators that verify the 2028 consensus

This piece is an industry and investment analysis based on publicly available information, and does not recommend buying or selling any specific stock. All investment decisions and their outcomes are the responsibility of the investor. The figures and schedules in the text include reports and industry estimates, and may differ from reality.

1. Why the Substrate Became the Problem

A semiconductor chip (the die) is a fingernail-sized piece of silicon, and the wiring on it is finer than a few hundredths of a human hair. For this chip to work, it has to exchange power and signals with the outside world, but the wiring on the mainboard the chip plugs into is thousands of times thicker than the chip’s own. The adapter that narrows this gap in stages is the package substrate.

Sometimes you insert one more layer between chip and substrate to relay the wiring density once more, and that layer is the interposer. TSMC’s current technology CoWoS (Chip-on-Wafer-on-Substrate), which binds an NVIDIA GPU and HBM into one package, is the representative case of using a silicon interposer.

For the past 30 years, the mainstream substrate was the organic substrate. The structure repeats a single operation to build fine wiring layers: on a core made by hardening plastic resin filled with glass fiber cloth, you stack a layer of insulating film called ABF and draw copper wiring. Because you stack layers this way, it is called build-up.

ABF stands for Ajinomoto Build-up Film. It was originally the name of one specific product from Japan’s Ajinomoto, but as the company came to dominate the market, the name hardened into a generic term for build-up film itself.

The organic substrate is a cheap and mature technology, but the arrival of AI chips ran it into two physical limits.

The first is warpage.

Chip and substrate have different thermal expansion coefficients. The coefficient of thermal expansion (CTE) is a number for how much a material stretches when temperature rises by one degree, and silicon barely stretches while plastic stretches a lot.

Making a package involves bonding chip and substrate at over 200 degrees and then cooling them, and during this the two materials shrink at different rates, warping the whole package like a potato chip. When packages were small it was tolerable.

But AI accelerator packages have grown to well over 50mm on a side, and warpage worsens non-linearly as area grows. On a warped substrate, some of the tens of thousands of fine joints connecting chip and substrate lift or break, and that is yield loss.

The second is area itself.

There is a ceiling on the area a lithography tool can print in a single shot when it carves circuit patterns with light. This area, commonly called the reticle limit, is around 26 x 33mm, about 858 square millimeters.

AI accelerators crossed this limit long ago, so they stitch multiple dies together into one enormous package. TSMC’s package area roadmap moves from 5.5x the reticle to 9.5x and then 14x. At 9.5x, that comes to roughly 8,000 square millimeters, a square about 9 centimeters on each side. Once the package grows this much, it is no longer a matter of swapping the material alone. The very plate the package is made on has to go bigger. And the moment you enlarge the plate, the shape of the plate rises as a new problem.

Semiconductor packaging has so far been done on round silicon wafers, which is called wafer-level packaging, WLP (Wafer-Level Packaging) for short. But make a giant square package on a 300mm-diameter round wafer and the geometry problem of filling a round plate with a large square wastes the edges in bulk.

So the idea of making them on a square plate from the start is panel-level packaging, PLP (Panel-Level Packaging). Fill a square panel with square packages and area utilization rises above 75 percent, and processing more chips at once is favorable for throughput and unit cost. In the end the area limit is solved by going to a larger square panel.

Here the two threads meet at glass.

Warpage is a problem that needs a material change, and area is a problem that needs going to a larger square panel, and glass satisfies both conditions at once.

Depending on composition you can tune its CTE close to silicon, which reduces warpage at the root, and its surface is incomparably flatter than organic material, which lets you lay finer wiring.

At the same time, making and handling large square glass panels is what the display industry has done for decades, so the large-area manufacturing infrastructure that PLP needs already exists.

TSMC’s next-generation packaging CoPoS(Chip-on-Panel-on-Substrate), which we will cover shortly, is exactly this PLP family, and PLP is itself the channel through which glass enters packaging in earnest. The weakness is that glass is brittle, and this brittleness becomes the root of the yield and customer qualification story to come.

That answers why glass appeared.

But what actually matters to an investor is not that glass is good, it is which spot inside the package glass takes. Carrier, core, or interposer, the choice completely changes which company gets the money and when that money arrives.

2. The Four Kinds of Glass Mixed Inside the Phrase “Glass Substrate”

Glass is used in four places in packaging, and the investment judgment starts with telling these four apart.

First, the glass core substrate.

It is the original owner of the phrase “glass substrate,” and it is what Absolics, Samsung Electro-Mechanics, and Intel make. The structure is a three-layer sandwich. A glass core sits in the middle, with ABF build-up layers stacked on both faces.

In other words, what glass replaces is not ABF but the core of the organic substrate, the plastic core filled with glass fiber cloth. The ABF build-up goes on top of the glass core as before, in fact more precisely, and the chip attaches to the ABF surface, not the glass.

To electrically connect the wiring of the upper and lower ABF layers, you need a passage through the glass core, and that is the TGV (Through-Glass Via). It is a process of drilling hundreds of thousands of holes finer than a hair through the glass and filling them with copper.

But glass is a material that cracks, so the conventional methods of drilling or etching it away with gas like silicon do not work. Mishandle it and a fine crack forms, and that one crack turns the whole panel into a reject.

So what emerged is a two-stage method: first weakly mark the spots to be processed inside the glass with a laser, then cleanly dissolve only those spots with chemicals to open the holes. Who can do this process stably, fast, and at high yield is the first gate of glass substrate volume production, and the companies in the world that can implement it as equipment can be counted on one hand.

Even after the holes are drilled, hard problems remain. Copper fill and metallization, always cited as the technical hurdles of glass substrates, are exactly this. Glass has a smooth surface so copper does not stick well, and filling deep, fine holes with copper leaving no voids is the limit of plating technology. Form even one bubble while filling and that spot becomes an electrical weak point.

Second, the glass interposer.

This is the track that changes the interposer itself from silicon to glass, rather than the substrate. The 600 x 600mm sample Rapidus unveiled at SEMICON Japan 2025 is on this side, and Samsung Electro-Mechanics runs a two-track effort developing both glass core and glass interposer.

An interposer has to be far thinner than a substrate and its CTE requirements are stricter, so its technical difficulty is rated a notch above the core substrate. Its application position, competitive landscape, and volume timing all differ from the glass core substrate. It is a separate game.

Third, the temporary carrier.

This is the support glass that holds the chips and wiring layers flat during the process. It is removed once the process ends and does not remain in the final product, but as long as PLP runs, it is the earliest and most certain glass demand to occur.

The CoPoS distinction noted in the introduction comes precisely from here. In TSMC’s next-generation panel packaging CoPoS (Chip-on-Panel-on-Substrate, a structure where chips sit on a panel and that panel sits on a substrate), the glass whose spot is currently most solid is on the carrier side.

Per Ming-Chi Kuo’s June industry check, CoPoS uses a 310 x 310mm glass carrier, and at the volume stage a structure that processes a 510 x 515mm glass panel into a glass core substrate is also floated. But core substrate adoption is closer to industry check and estimate than confirmation.

Taiwanese industry press classifies the glass replacement of the silicon interposer as a long-term task, and what TSMC has officially confirmed extends only to the direction of panel transition and the use of glass material. The question of what substrate CoPoS’s early volume runs use remains open, and this is one of the checkpoints addressed later.

Fourth, T-glass, the glass fiber cloth.

Nittobo’s T-glass, which became a talking point for shortages starting last year, is an entirely different thing from the three above. It is low-thermal-expansion glass drawn into threads and woven into cloth, and it goes inside the plastic core of the existing organic substrate to lock in stiffness and dimensional stability.

Nittobo holds roughly 90 percent of this market, and reports have followed of NVIDIA, AMD, and Big Tech executives visiting in person to secure volume.

Here the relationship between the fourth and the first is the most common and expensive point of confusion from an investment standpoint. T-glass is a thing that benefits the more organic substrates sell, while the glass core substrate is the technology that lifts that organic core out entirely. They are grouped under the same glass theme, but their mechanisms point in opposite directions.

The T-glass bottleneck is happening now, while glass core penetration is 2027 at the earliest. While Nittobo proceeds with expanding its Fukushima base targeting 2027 operation (up to three times per reports) and prepares a next-generation T-glass launch in 2028, glass core is only now about to pass its first customer qualification.

That these two, different in direction and different in clock, sit in the same basket means the stocks now grouped under the glass theme are actually riding different cycles. So where in the value chain, to whom, and in what order do these four kinds of glass send the money flowing? And before that money arrives, what should you confirm as the signal? The answer reveals itself by following how far commercialization has come and in what order the money arrives at each spot.